1. Field of the Invention
The invention relates in general to a power state management system and method thereof, and more particularly to a PCI Express link state (L-state) management system and method thereof.
2. Description of the Related Art
Along with technology progress, the mainstream peripheral component interconnect (PCI) of personal computers has becoming too narrow in transmission bandwidth to meet the requirement of processors and output/input devices in the future. Therefore, industrials supply a new generation of PCI Express as a standard field input/output bus for various operation platforms in the future. The main feature of PCI Express lies in the increase of performance where the single transmission rate can reach 2.5 GHz. The transmission rate can be further improved by increasing the number of lanes, such as using 4 lanes to reach 4 times of transmission rate.
The advanced configuration and power interface (ACPI) defines the power states in various situations, which are called device power states or D-states, and PCI Express further defines the power states of the links among devices, which are called link states or L-states. Besides, the link states have also corresponding relationship with the device power states.
The device power state Do represents the device operates in a normal state. When the devices are set in the D0 state, the link among the devices is set in a link state L0, L0s or L1.
The device power states D1 and D2 are not defined clearly. Generally speaking, these two states save less electric power but maintain more device states. The D1 and D2 states correspond to the link power state L1.
The device power state D3 implies a power off state, which includes D3cold and D3hot states. When a device is in the D3cold state, it implies the main power is not supplied to the device. When the device is in the D3hot state, it implies the main power is still supplied to the device. When the power state of devices is D3cold, if some auxiliary power is supplied to the devices, the link among the devices corresponds to a link state L3. The device power state D3hot corresponds to the link state L1 or L2/L3 ready.
The link state L0 defines the link among devices is in normal operation. During the data transmission of the link among devices, if there exists temporary idle periods, the system can enter the link state L0s to reduce power consumption.
When the link among devices is set in the link state L1, the devices have no operation requirement, and thus the required electrical power for the link among the device can be reduced. In the meanwhile, no clock signal is triggered and the phase locked loop (PLL) is also paused.
The link states L2 and L3 are both power-off states. The link state L2 has auxiliary power but the link state L3 has none.